1. Field of the Invention
This invention relates to a semiconductor integrated circuit constructed with MOS transistors, and more particularly to a latch circuit and a shift register, which are used in the output stage of an image memory.
2. Description of the Related Art
An operation speed of the image memory is very high. For example, a cycle time of the image memory is approximately several tens ns. A latch circuit for the data outputting must be operable at a high speed and with a good reliability.
A conventional data output latch circuit in use with an image memory is as illustrated in FIG. 1. The latch circuit is comprised of first latch section 10 and second latch section 20. First latch section 10 includes clocked inverter 11 controlled by a pair of clock signals .phi. and .phi., and flip-flop 14 coupled at the input terminal with the output terminal of clocked inverter 11. Flip-flop 14 is made up of complementary type inverter 12 and clocked inverter 13. Clocked inverter 13 is coupled at the input terminal with the output terminal of inverter 12 and at the output terminal with the input terminal of the inverter, and is controlled by a pair of clocked signals .phi. and .phi.. Second latch section 20 includes clocked inverter 21 controlled by clock signals .phi. and .phi., and flip-flop 24 connected at the input terminal with the output terminal of clocked inverter 21. Flip-flop 24 is made up of complementary type inverter 22 and clocked inverter 23. Clocked inverter 23 is connected at the input terminal with the output terminal of inverter 22, and at the output terminal with the input terminal of the inverter, and is controlled by clock signals .phi. and .phi.. Input signal Vin is directly input to latch section 10. Input signal Vin is also input to latch section 20, after passed through and inverted by inverter 25. The output terminal of latch section 10 is connected to the gate of N channel MOS transistor 27 as a load transistor, which partially constitutes output circuit 26. The output terminal of latch section 20 is connected to the gate of N channel MOS transistor 28 as a drive transistor.
The details of latch section 10 or 20 are illustrated in FIG. 2. Clock signal .phi. is applied to the gate of N channel MOS transistor QN2 as a switching transistor for clocked inverter 11 and the gate of P channel MOS transistor QP4 as a switching transistor for clocked inverter 13. Clock signal .phi. is applied to the gate of P channel MOS transistor QP2 as a switching transistor in clocked inverter 11 and the gate of N channel MOS transistor QN4 as a switching transistor in clocked inverter 13.
The operation of the data output latch circuit of FIG. 1 thus arranged will be described.
In a first period, clock signal .phi. is in high ("H") level and clock signal .phi. is in low ("L"level. Clocked inverters 11 and 21 execute the inverter operation, to invert and delay input signals Vin, and produce output signals Q and Q.
In a second period, clock signal .phi. is changed from "H" to "L" in logical level, and clock signal .phi. is changed from "L" to "H". Clocked inverters 11 and 21 do not execute the inverter operation, while clocked inverters 13 and 23 execute the inverter operation. As a result, the data thus far output are stored in flip-flops 14 and 24.
In a third period, clock signal .phi. is "L" in logical level and clock signal .phi. is "H" in logical level. At this time, flip-flops 14 and 24 are operating, and hence continue to store the data therein. In this case, clocked inverters 11 and 21 do not operate. Accordingly, output signals Q and Q remain unchanged, even if input signal Vin varies.
In a fourth period, clock signal .phi. is changed from "L" to "H", and clock signal .phi. is changed from "H" to "L". Clocked inverters 13 and 23 do not operate, while clocked inverters 11 and 21 operate to execute the inverter operation. Then, the latch sections 10 and 20 fetch new input signal Vin, and substantially simultaneously output the contents of the input signals, i.e., the data stored therein as output signals Q and E,ovs/Q/ .
A sequence of the operations of the first to fourth periods is repeated.
A timing chart illustrating the sequence of operations of the FIG. 1 circuit is shown in FIG. 3.
As described above, the conventional latch circuit uses the clocked inverters. Use of the clocked inverters needs opposite phase clock signals .phi. and .phi. controlling this inverter. Practically, however, it is very difficult to generate the clock signals which are exactly out of phase in a continuous manner. To form such clock signals, a clock signal must be passed through an inverter. When passing through the inverter, the clock signal inevitably delays by some time-length. Therefore, the clock signal and the inverted clock signal propagate and reach a point at different times. If such staggered clock signals are applied to the clocked inverter, the clocked inverter is placed in a high impedance state during a transient period that the input-signal outputting mode is changed to the output-signal holding mode. This high impedance state is peculiar to the clocked inverter. In such a high impedance state, the output data is possibly inverted, leading to a malfunction operation of the inverter.
Why the high impedance state occurs in the clocked inverter and what the phenomenon brings about, will be described below.
In FIG. 2, when input signal Vin is 37 H", clock signal .phi. is "H", and inverted clock signal .phi. is 37 L", MOS transistors QN1, QN2, and QP2 are turned on, while transistors QP1, QP4 and QN4 are turned off. Accordingly, node NA is "L", transistor QP5 is turned on, and transistor QN5 is turned off, output Q provides an "H" level signal, transistor QP3 is turned off, and transistor QN3 is turned on.
If clock signals .phi. and .phi. are both "L" while input signal Vin is kept high, then MOS transistors QP1, QP3 and QN2, and QN4 are turned off, and transistors QP2, QP4, QN1 and QN3 are turned on. Under this condition, both the clocked inverters 11 and 13 do not operate, and node NA is at high impedance. At the initial stage in the operation, node NA maintains the previous potential, i.e., "L" level. At this time, the transistors QP2 and QP4 in the clocked inverter are in an on state. If the potential at node N3 is high, the high potential is transferred to node NA, so that the potential at node NA goes high. If the potential increase is large, transistor QP5 is turned off, and transistor QN5 is turned on. Finally, the logical state at output Q is inverted.
When input signal Vin is "L", clock signal .phi. is "H", and clock signal .phi. is "L", MOS transistors QP1, QP2 and QN2 are turned on, and transistors QN1, QN4 and QP4 are turned off. Accordingly, the potential at node NA goes high. Transistor QP5 is turned off, and transistor QN5 is turned on. Output Q provides an "L" level signal. Then, transistor QP3 is turned on and transistor QN3 is turned off.
While input signal Vin maintains the "L" state, clock signals .phi. and .phi. go high. Then, MOS transistors QP1, QP3, QN2 and QN4 are turned on, and transistors QP2, QP4, QN1 and QN3 are turned off. Under this condition, clocked inverters 11 and 13 do not operate, and node NA is at a high impedance. At the initial stage in the operation, node NA maintains the previous potential, i.e., an "H" state. At this time, the transistors QN2 and QN4 in the clocked inverter are in an on state. If the potential at node N4 is low, the low potential is transferred to node NA, so that the potential at node NA goes low. If this potential drop is large, MOS transistors QP5 is turned on, and transistor QN5 is turned off. Finally, the logical state of the data at output Q is inverted.
Latch sections 10 and 20 are followed by output circuit 26, as shown in FIG. 1. Output circuit 26 is made up of N channel MOS transistor 27 as a load transistor and N channel MOS transistor 28 as a drive transistor. The gates of these transistors 27 and 28 are controlled by the output signals Q and Q of latch sections 10 and 20. With such a circuit arrangement, when the output potential is inverted as described above, load transistor 27 and drive transistor 28 are both in an on state, so that a rush-current flows between the power source terminals. With this rush-current, the power dissipation is greatly increased, particularly when the memory device including the output circuit operates at a high speed. This further provides an instable power source voltage of the device.
Further, even if clock signals .phi. and .phi. are perfectly opposite phase, and the level variations simultaneously occur at both the outputs Q and Q, it is impossible to prevent the rush-current from flowing in the output circuit 26 during this transient period.
Particularly in the image memory in which the serial access is performed with a short cycle time, the increased power dissipation due to the rush-current is not negligible.